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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Low Voltage PLL Clock Driver
The MPC9952 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock tree applications. The device features a fully integrated PLL with no external components required. With output frequencies of up to 180MHz and eleven low skew outputs the MPC9952 is well suited for high performance designs. The device employs a fully differential PLL design to optimize jitter and noise rejection performance. Jitter is an increasingly important parameter as more microprocessors and ASiC's are employing on chip PLL clock distribution.
MPC9952
LOW VOLTAGE PLL CLOCK DRIVER
* * * *
Fully Integrated PLL Output Frequency up to 180MHz High Impedance Disabled Outputs Compatible with PowerPCTM, Intel and High Performance RISC Microprocessors
* Output Frequency Configurable * LQFP Packaging * 100ps Cycle-to-Cycle Jitter
The MPC9952 features three banks of individually configurable outputs. The banks contain 5 outputs, 4 outputs and 2 outputs. The internal divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1 and 3:2:1. The output frequency relationship is controlled by the fsel frequency control pins. The fsel pins as well as the other inputs are LVCMOS/LVTTL compatible inputs.
FA SUFFIX LQFP PACKAGE CASE 873A-02
The MPC9952 uses external feedback to the PLL. This features allows for the use of the device as a "zero delay" buffer. Any of the eleven outputs can be used as the feedback to the PLL. The VCO_Sel pin allows for the choice of two VCO ranges to optimize PLL stability and jitter performance. The MR/OE pin allows the user to force the outputs into high impedance for board level test. For system debug the PLL of the MPC9952 can be bypassed. When forced to a logic HIGH, the PLLEN input will route the signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it may take several transitions of the RefClk to affect a transition on the outputs. This features allows a designer to single step the design for debug purposes. The outputs of the MPC9952 are LVCMOS outputs. The outputs are optimally designed to drive terminated transmission lines. For applications using series terminated transmission lines each MPC9952 output can drive two lines. This capability provides an effective fanout of 22, more than enough clocks for most clock tree designs. For more information on driving transmission lines consult the applications section of this data sheet.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
03/01
(c) Motorola, Inc. 2001
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REV 2
MPC9952
Figure 1. MPC9952 Logic Diagram
PLL_En
REFCLK PHASE DETECTOR FBin Qa2 LPF VCO_Sel fsela
(Int Pull Down) (Int Pull Down)
VCO 200-480MHz
/2
/4//6
Qa0 Qa1
Qa3 Qa4
/4//2
Qb0 Qb1 Qb2
fselb
(Int Pull Down)
Qb3
/2//4 fselc MR/OE
(Int Pull Down) (Int Pull Down)
Qc0 Qc1
GNDO
GNDO
VCCO
VCCO
Qb1
Qb0
Qa4
Qa3
FUNCTION TABLES
24 VCCO Qb2 Qb3 GNDO GNDO Qc0 Qc1 VCCO 25 26 27 28 23 22 21 20 19 18 17 16 15 14 13 VCCO Qa2 Qa1 GNDO Qa0 VCCI VCCA PLL_En Pin Name VCCA 32 1 2 3 4 5 6 7 8 9 VCCO VCCI GNDI VCO_Sel REFCLK MR/OE GNDI fselb fsela FBin fselc GNDO Description PLL Power Supply Output Buffer Power Supply Internal Core Logic Power Supply Internal Ground Output Buffer Ground Control Pin VCO_Sel MR/OE 12 11 10 PLL_En Logic `0' fVCO Output Enable Enable PLL Logic `1' fVCO/2 High Z Disable PLL fsela 0 1 Qan /4 /6 fselb 0 1 Qbn /4 /2 fselc 0 1 Qcn /2 /4
MPC9952
29 30 31
Figure 2. 32-Lead Pinout (Top View)
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TIMING SOLUTIONS DL207 -- Rev 0
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ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 4.6 VCC + 0.3 20 125 Unit V V mA C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
THERMAL CHARACTERISTICS Proper thermal management is critical for reliable system operation. This is especially true for high fanout and high drive capability products. Generic thermal information is available for the Motorola Clock Driver products. The means of calculating die power, the corresponding die temperature and the relationship to longterm reliability is addressed in the Motorola application note AN1545. DC CHARACTERISTICS (TA = 0 to 70C, VCCO = VCCI = VCCA = 3.3V 5%)
Symbol VIH VIL VOH VOL IIN CIN Cpd ICC Characteristic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Maximum Quiescent Supply Current 2.7 25 160 2.4 0.5 120 4.0 Min 2.0 Typ Max 3.6 0.8 Unit V V V V A pF pF mA Total ICC Static Current IOH = -20mA (Note 1.) IOL = 20mA (Note 1.) Note 2. Condition
ICCA PLL Supply Current 15 20 mA 1. The MPC9952 outputs can drive series or parallel terminated 50 (or 50 to VCCO/2) transmission lines on the incident edge (see Applications Info section). 2. Inputs have pull-up, pull-down resistors which affect input current.
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70C)
Symbol tr, tf fref Characteristic TCLK Input Rise/Falls Reference Input Frequency Min Max 3.0 100 Unit ns MHz % Note 3. Condition
frefDC Reference Input Duty Cycle 25 75 3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
TIMING SOLUTIONS DL207 -- Rev 0
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MPC9952
AC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 5%)
Symbol tr, tf tpw tos Characteristic Output Rise/Fall Time (Note 4.) Output Pulse Width (Note 4.) Output-to-Output Skew (Note 4.) PLL VCO Lock Range Maximum Output Frequency Qc,Qb (/2) Qa,Qb,Qc (/4) Qa (/6) Excluding Qa0 All Outputs All Outputs 200 180 120 80 -200 2 2 100 0 200 8 10 Min 0.10 tCYCLE/2 -750 tCYCLE/2 500 Typ Max 1.0 tCYCLE/2 +750 350 450 550 480 Unit ns ps ps Same Frequencies Same Frequencies Different Frequencies Note 6. Note 4. Condition 0.8 to 2.0V
fVCO fmax
MHz MHz
tpd tPLZ, tPHZ tPZL, tPLH tjit(cc)
REFCLK to FBIN Delay Output Disable Time Output Enable Time Cycle-to-Cycle Jitter
ps ns ns ps
Notes 4., 5. Note 4. Note 4.
tlock Maximum PLL Lock Time 10 ms 4. Termination of 50 to VCCO/2. 5. tpd is specified for 50MHz input ref, the window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods. The tpd does not include jitter. 6. The PLL may be unstable with a divide by 2 feedback ratio.
APPLICATIONS INFORMATION
Driving Transmission Lines The MPC9952 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of approximately 7 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091.
MPC9952 OUTPUT BUFFER IN 7 RS = 43 ZO = 50 OutA
technique terminates the signal at the end of the line with a 50 resistance to VCCO/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9952 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9952 clock driver is effectively doubled due to its capability to drive multiple lines. The waveform plots of Figure 4 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC9952 output buffers is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9952. The output waveform in Figure 4 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
MPC9952 OUTPUT BUFFER IN 7
RS = 43
ZO = 50 OutB0
RS = 43
ZO = 50 OutB1
Figure 3. Single versus Dual Transmission Lines In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel
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TIMING SOLUTIONS DL207 -- Rev 0
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technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC9952.
3.3V 1.0 RS=5-15 VCCA 0 2 4 6 8 TIME (nS) 10 12 14 VCC 22F MPC9952 0.01F
3.0 OutA tD = 3.8956 OutB tD = 3.9386
2.5
VOLTAGE (V)
2.0 In 1.5
0.5
Figure 4. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9952 OUTPUT BUFFER 7 RS = 36 ZO = 50
0.01F
Figure 6. Power Supply Filter Figure 6 illustrates a typical power supply filter scheme. The MPC9952 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC9952. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.3V - 5% must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 6 must have a resistance of 5-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9952 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs.
RS = 36
ZO = 50
7 + 36 k 36 = 50 k 50 25 = 25 Figure 5. Optimized Dual Line Termination Power Supply Filtering The MPC9952 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC9952 provides separate power supplies for the output buffers (VCCO) and the internal PLL (VCCA) of the device. The purpose of this design
TIMING SOLUTIONS DL207 -- Rev 0
5
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MPC9952
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25
4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
CE
SECTION AE-AE
X DETAIL AD
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GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
6
TIMING SOLUTIONS DL207 -- Rev 0
-T-, -U-, -Z-
EE EE EE
MPC9952
NOTES
TIMING SOLUTIONS DL207 -- Rev 0
7
MOTOROLA
MPC9952
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TIMING SOLUTIONS MPC9952/D DL207 -- Rev 0

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